Publications
1. Prof. S Gurunarayanan:
Journals:
1. Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan, Design of an MTJ/CMOS based Asynchronous System for Ultra-Low Power Energy Autonomous Applications, Journal of Circuits, Systems and Computers, June, 2020. doi: 10.1142/S0218126621500584
2. G.S.S. Chalapathi, Vinay Chamola, Chen-Khong Tham, S. Gurunarayanan and Nirwan Ansari “An Optimal Delay Aware Task Assignment Scheme for Wireless SDN Networked Edge Cloudlets” Future Generation Computing Systems. vol. 102, pp. 862-875, Jan 2020
3. G.S.S Chalapathi, Vinay Chamola, S Gurunarayanan and Biplab Sikdar, “E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster-based Wireless Sensor Networks,” IEEE Sensors Journal, vol. 19, no. 21, pp. 10144-10156, 1 Nov.1, 2019.
4. G.S.S Chalapathi, Vinay Chamola and S Gurunarayanan, “A Testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT,” Journal of Intelligent and Fuzzy Systems, IOS Press, vol. 36, no. 5, pp. 4531-4543, 2019
5. G.S.S Chalapathi, Bernhard Etzlinger, S Gurunarayanan and Andreas Springer, “Integrated Cooperative Synchronization for Wireless Sensor Networks,” IEEE Wireless Communication Letters, vol. 8, no. 3, pp. 701-704, June 2019.
6. D.C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, and Abhijeet Nawal ," Global Scheduling Heuristics for Multicore Architecture", Hindawi Publishing Corporation, Scientific Programming, Volume 2015, Article ID 860891 , http://dx.doi.org/10.1155/2015/860891
7. D.C. Kiran, S. Gurunarayanan, J.P.Misra & Munish Bhathia "Register Allocation for Fine Grained Threads on Multicore Processors". Journal of King Saud University - Computer and Information Sciences, Elsevier,Volume 27, Issue 3 2015. https://core.ac.uk/download/pdf/82071516.pdf
8. Nitin Chaturvedi, Arun Subramanian, S Gururnarayanan, “Selective cache line replication scheme in Shared Last Level Cache”, in Procedia of Computer Science, Elsevier, Volume 46, pp.1095-1107, 2015. (Scopus)
9. Nitin Chaturvedi, Arun Subramanian, S Gururnarayanan, “ An Efficient data access policy for shared last Level Cache”, in WSEAS transaction on computers, Volume 14, 2015.
10. Nitin Chaturvedi, S Gurunaryanan, “An Efficient adaptive block pinning for multi-core architectures”, in Journal of Microprocessor and Microsystems, Elsevier, Volume 39, Issue 3, 2015. (SCI)
11. Nitin Chaturvedi, S Gurunaryanan “An Adaptive Migration-Replication Scheme (AMR) for Shared Cache in Chip Multiprocessors” in Journal of Parallel Computing, Springer, Volume 71, Issue 10 pp. 3904-3933, Oct. 2015. (SCI)
12. Nitin Chaturvedi, S Gurunaryanan “An A Locality-Aware Variable Granularity Cache Architecture” Electronics Letter- IET, January 2015
13. Nitin Chaturvedi, S Gururnarayanan, “ Adaptive Block Pinning : A Novel Shared Cache Partitioning Techniques for CMP” in European Journal of Scientific Research, Volume 117, Issue 1, June 2014.
14. Nitin Chaturvedi, S Gururnarayanan, “ Study of Various Factors Affecting Performance of Multi-Core Architectures” in International Journal of Distributed and Parallel Systems, Volume 4, No 4, July 2013.
15. Jai Gopal Pandey, Abhijit Karmakar, Chandra Shekhar and S. Gurunarayanan “Platform - Based Design Approach for Embedded Vision Applications”Journal of Image and Graphics Volume 1, No.1, March 2013.
16. Nitin Chaturvedi, Jithin Thomas, S Gururnarayanan, “ Adaptive Block Pinning Based : Dynamic Cache Partitioning for Multi - Core Architectures” in International Journal of Computer Science & Information Technology (IJCSIT), Volume 2, No 6, December 2010.
17. Nitin Chaturvedi, Jithin Thomas, S Gururnarayanan, “Adaptive Zone-Aware Multi-bank on Chip last level L2 cache Partitioning for Chip Multiprocessors” in International Journal of Computer Applications ,Volume 6, No-9, September 2010.
18. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Cache Memory Design with Late Replacements for Embedded Systems” International Journal of Lateral Computing, Vol.2, No. 2, August 2006.
19. A K Singh, S Gurunarayanan, V Ramachandran and M Umashankar. “Edge Potential Effects on the operation of short channel devices” Microelectronics International Vol.20, Number 3, 2003
Conferences:
1. Pranshu, Shaishta, Nitin, S Gurunarayanan, “An Exploration of Neuromorphic Systems and Related Design Issues/Challenges in Dark Silicon Era” in 3rd International Conference on Communication Systems, ICCS-2017, 14-16 October 2017, Pilani, India.
2. Suvi Jain, Nitin Chaturvedi, S Gurunarayanan, “Design and Analysis of 6T SRAM Cell with NBL Write Assist Technique Using FinFET” in International Conference on Computer, Communications and Electronics, COMPTELIX 2017, 1-2 July 2017,Jaipur,India .(IEEE-Xplore)
3. Divya Suneja, Nitin Chaturvedi, S Gurunarayanan, “A Comparative Analysis of Read/Write Assist Techniques on Performance & Margin in 6T SRAM Cell Design” in International Conference on Computer, Communications and Electronics, COMPTELIX 2017, 1-2, July 2017, Jaipur, India (IEEE -Xplore)
4. Nikunj, Nitin Chaturvedi, S Gurunarayanan, “Design Of Non-Volatile Asynchronous Circuit Using CMOS-FDSOI/FinFET Technologies” in IEEE International Conference on Computing, Analytics and Security Trends, CAST-2016, 19-21 December 2016, Pune, India (IEEE-Xplore)
5. Pranshu, Shaishta, Nitin Chaturvedi, S Gurunarayanan, “An Investigation of Power- Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems” in 2nd IEEE International symposium on nanoelectronic and information systems, IEEE-INIS-2016, 19-21 December 2016, IIITM Gwalior,India (IEEE-Xplore)
6. GSS Chalapathi, R. Manekar, V. Chamola, K.R. Anupama and S Gurunarayanan, "Hardware
Validated Efficient Simple Time Synchronization Protocol for clustered WSN," IEEE TENCON, 2016, Singapore, Nov. 22- 25, 2016.
7. R. Manekar, GSS Chalapathi, V. Chamola, K.R. Anupama and S Gurunarayanan,
“A Simple Time Synchronization Algorithm for WSNs in Smart Grid Applications,”
IEEE Symposium on Emerging Topics in Smart and Sustainable Grids, Singapore, Sept. 2016
8. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, An Embedded Frame work
for Accurate Object Localization using Center of Gravity Measure with Mean Shift Procedure, IEEE 19th International Symposium on VLSI Design and Test,
Ahmedabad, India, 26-29 June 2015, pp. 1-6.
8.
9. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “Architectures for Embedded Vision Application using FPGA-based Platform” IEEE 28th Int’l Conf. on VLSI Design and 14th Int’l Conf. on Embedded Systems (VLSI Design 2015), Bangalore, India, 3-7 Jan. 2015.
10. J.G. Pandey, A Karmakar, C Shekhar, S Gurunarayanan, “An FPGA-based architecture for local similarity measure for image/video processing applications” 2015, 28th International Conference on VLSI Design, 339-344, Bangalore, India.
11. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, Architectures and algorithms for image and video processing using FPGA-based platform IEEE 18th International Symposium on VLSI Design and Test, Coimbatore, India,16-18 July 2014 pp.1-1
12. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “A novel architecture for FPGA implementation of Otsu’s global automatic image thresholding algorithm,” in Proceedings of IEEE 27th International Conf. on VLSI Design and 13th International Conf. on Embedded Systems (VLSI Design 2014), Mumbai, India, 5-9 Jan. 2014, pp. 300-305. (IEEE Xplore) [Impact factor: 0.40] (For Year 2012)
13. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based architecture for kernel-smoothed local histogram computation,”Accepted for publication in IEEE International Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, 01-05 June, 2014. (IEEE - Xplore) [Impact factor: 0.27] (For Year 2012).
14. J. G. Pandey, A. Karmakar, A. K. Mishra, C. Shekhar, and S. Gurunarayanan, “Implemention of an improved connected component labeling algorithm using FPGA based platform,” Accepted for Publication in IEEE International Conf. on Signal Processing and Communications (SPCOM, 2014), IISc-Bangalore, India, 22-25 July 2014. (IEEE- Xplore)
15. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based novel architecture for the fixed-point binary antilogarithmic computation,” in Proceedings of IEEE International Conf. on Electronic Systems, Signal Processing and Computing Technologies (ICESC), Nagpur, India, 09-11 Jan. 2014, pp. 23-28. (IEEE- Xplore) [Best Paper Award]
. 16. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based
fixed-point architecture for binary logarithmic computation,” in
Proceedings of 2nd IEEE International Conf. in Image Information Processing (ICIIP-2013),
Shimla, India, 09-12 Dec. 2013, pp. 383- 388. (IEEE -Xplore)
17. Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-Core Architectures” 2013 IEEE International Conference on Computational Intelligence and Communication Network, ICCN- 2013, September 27-29, 2013, Mathura, India (IEEE –Xplore)
18. Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Cache Coherence Protocol with adaptive Cache for Multi-core Architectures” in proceedings of International Conference on Advanced Electronic Systems, ICAES-2013 September 21-23, 2013, CEERI, Pilani,India (IEEE –Xplore)
19. Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on Multicore Processors: Cores With Multiple Functional Units". Compute '13: Proceedings of the 6th ACM India Computing Convention, Vellore, Tamilnadu, India. August 2013 Article No.: 20 Pages 1–6 . https://doi.org/10.1145/2522548.2523137. http://dl.acm.org/citation.cfm? doid=2522548.2523137
20. D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February 2013. https://ieeexplore.ieee.org/document/6621400
21. D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Compiler Driven Inter Block Parallelism for Multicore Processors. In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, Bangalore, India, August 2012. http://link.springer.com/chapter/10.1007/978-3-642-31686-9_50
22. D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures. In The International Conference of Eco-friendly Computing and Communication Systems, (ICECCS) 2012, Kochi, India, August 9-11, 2012. Proceedings published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, pp.9-17 http://link.springer.com/chapter/10.1007%2F978-3-642-32112-2_2
23. D.C. Kiran, S. Gurunarayanan, J.P.Misra and Faizan Khaliq, An Efficient Method to Compute Static Single Assignment Form for Multicore Architecture. In 1st IEEE International Conference on Recent Advances in Information Technology, Dhanbad, India. March, 2012. pp. 776-789, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6194553
24. Nitin Chaturvedi, Prashant Gupta, S Gurunarayanan, “Efficient Cache Migration Policy for Chip Multi-Processors” 2011 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC-11, 15-18 December 2011. Kanyakumari, Tamilnadu, India.
25. D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Taming Compiler to Work with Multicore Processors. IEEE Conference on Process Automation, Control and Computing. Coimbatore, Tamilnadu, India 20-22 July 2011. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5978868
26. D.C.Kiran, B. Radheshyam. Gurunarayanan, and J.P.Misra, Compiler Assisted Dynamic Scheduling for Multicore Processors. IEEE Conference on Process Automation, Control and Computing, Coimbatore, Tamilnadu, India, July,20- 22, 2011. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5978903
27. Nitin Chaturvedi, Pradeep Harinderan, S Gururnarayanan, “A Novel shared L2 NUCA cache partitioning scheme for Multi-core Architectures” in proceedings of International Conference on Emerging Trends in Engineering (ICETE),Maharashtra, India, Feb.20-21, 2010. pp. 183-188.
28. Biju Raveendran , Sundar Balasubramaniam , and S. Gurunarayanan. “Evaluation of Priority Based Real Time Scheduling Algorithms: Choices and Tradeoffs.” In Proceedings of the 23rd Annual ACM Symposium on Applied Computing (ACM SAC'08), Brazil, Mar-2008, vol. 1, pp. 302 - 307.
29. Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and
S Gurunarayanan. “Predictive Placement Scheme for Set-Associative Cache for Energy Efficient Embedded System.” Proceedings of International Conference on Signal Processing, Communications and Networking, (ICSCN 2008),January 4-6, 2008, Chennai,
Tamilnadu, India pp. 152-157, Available online in IEEEXPLORE.
30. Biju Raveendran, T S B Sudarshan, Dlip Kumar, Priyanaka Tugudu and S Gurunarayanan. “LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache.”Proceedings of 15th IEEE International Conference On Advanced Computing (ADCOM), IIT-Kharagpur,India Dec-2007, pp. 339-344, Available online in IEEEXPLORE.
31. Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and S Gurunarayanan. “An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System.” Proceedings of ESA'07- The 2007 International Conference on Embedded Systems and Applications, USA, (Published by CSREA Press, Jun-2007, pp. 188–194.
32. Biju Raveendran, J P Misra, Karan Bhatnagar and S Gurunarayanan. “EFFS: Efficient Flash File System for Wireless Sensor Nodes.” Proceedings of ESA'07- The 2007 International
Conference on Embedded Systems and Applications, USA, (Published by CSREA Press,
Jun-2007, pp. 159– 165.
33. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Selective Placement Data Cache for Low Energy Embedded System”. Proceedings of 14th IEEE International Conference On Advanced Computing (ADCOM), NITK, Surathkal, India. Dec-20-23, 2006, pp. 473-476, Available online in IEE-EXPLORE.
34. Ninad B Kothari, T S B Sudarshan, S Gurunarayanan, and S Chandrashekhar. “SoC Design of a Low Power Wireless Sensor Network Node for Zigbee Systems.” Proceedings of 14th IEEE International Conference On Advanced Computing (ADCOM), NITK, Surathkal, India. Dec- 20-23-2006, pp. 462-466. Available online in IEE-EXPLORE.
35. Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “Variants of Priority Scheduling Algorithms for Reduced Context Switches in Real Time System.” 8th International Conference on Distributed Computing and Networking (ICDCN), Lecture Notes in Computer Science, Springer-Verlag. IIT - Guwahati, India. Dec-2006, pp. 466-478.
36. Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “A Context- Switch Reduction Heuristic for Power-Aware Off-line Scheduling.” 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC), Lecture Notes in Computer Science, Vol. 4186, Springer-Verlag. Shanghai, China, Sep-2006, pp. 404-411.
37. Ninad B Kothari, T S B Sudarshan, Shipra Bhal, Tejesh E C, and S Gurunarayanan. “Design of an Efficient Low-Power AES Engine for Zigbee Systems.” Proceedings of 10th IEEE VLSI Design & Test Symposium (VDAT), Goa, India. Aug-2006, pp. 264-272.
38. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Cache Memory Design with Late Replacements for Embedded Systems.” Proceedings of 2nd International Conference on Embedded Systems, Mobile Communication and Computing (ICEMC2), Bangalore, India. Aug- 2006, pp. 76- 90.
39. Gurunarayanan , R Mehrotra and S Chandrashekhar. “Modelling of ESD Protection Circuits.”Proceedings of 8th International Workshop on Physics of Semiconductor
Devices, New Delhi, India. 1995.
40. Gurunarayanan , R Mehrotra and S Chandrashekhar.”Drain Induced Barrier lowering in short channel NMOS Devices.”Proceedings of 7th International Workshop on Physics of Semiconductor Devices. New Delhi, India Dec. 14-18, 1993. 75-76. Narosa Publishing House, 1994
2. Prof. Anu Gupta:
Journals:
[32] Harjap Singh Saini and Anu Gupta, "Constant Power Consumption Design of Novel Differential Logic Gate for Immunity against Differential Power Analysis", IET Circuits, Devices & Systems (accepted for publication) --SCI Indexed, SCI-E, Scopus, IET Inspec , EI Compendex, Impact Factor: 1.308 CiteScore: 1.49. SNIP: 1.014
[31] Vineet Kumar, Abhijit Asati and Anu Gupta, “Memory-Efficient Architecture of Circle Hough Transform and Its FPGA Implementation for Iris Localization,” IET Image Processing, April 2018, DOI: 10.1049/iet-ipr.2017.1167,Online ISSN 1751-9667), (Impact factor: 1.044) -- SCI Indexed, SCI-E, Scopus, IET Inspec, EI Compendex
[30] Anu Gupta Priya Gupta, and Abhijit Asati, "Novel Low Power and Stable SRAM Cells for Subthreshold operation at 45 nm" International Journal of Electronics, February 2018. (DOI:10.1080/00207217.2018.1440437) --SCI, SCI-E, Scopus,Web of Science Indexed
[29] Vineet Kumar, Abhijit Asati and Anu Gupta,"Low-Latency Median Filter Core for Hardware Implementation of 5-by-5 Median Filtering," IET Image Processing, August 2017, (doi: 10.1049/iet-ipr.2016.0737, impact Factor: 1.044) -- SCI Indexed
[28] Vineet Kumar, Abhijit Asati, Anu Gupta, “Hardware Accelerators for Iris Localization”, Springer Journal of Signal Processing Systems, September 2017. ( DOI 10.1007/s11265-017-1282-2, Impact factor:0.893) -- SCI-E Indexed
[27] Vineet Kumar, Abhijit Asati and Anu Gupta, "Hardware implementation of a novel edge-map generation technique for pupil detection in NIR Images," Elsevier Journal Engineering Science and Technology, an International Journal (JESTEC), November 2016, (DOI information: 10.1016/j.jestch.2016.11.001) -- Scopus Indexed
[26] Vineet Kumar, Abhijit Asati and Anu Gupta, “Accurate iris localization using edge map generation and adaptive circular Hough transform for less constrained infrared iris images,” Int. Journal of Electrical and Computer Engineering, IAES publication, Indonesia, Vol. 6, No.4, pp. 1637-1646, August 2016. (SNIP: 1.090, H index:8) -- Scopus Indexed
[25] Vineet Kumar, Abhijit Asati and Anu Gupta, “A novel edge-map creation approach for highly accurate pupil localization in unconstrained infrared iris images”, Journal of Electrical and Computer Engineering, Hindawi publishing corporation Vol. 2016, Article ID 4709876, May 2016. (http://dx.doi.org/10.1155/2016/4709876) (H index:14) -- Scopus Indexed
[24] Priya Gupta, Ishan Munje, Anu Gupta and Abhijit Asati, "Effectiveness of body bias and hybrid logic: an energy efficient approach to design adders in sub-threshold regime," International Journal of Circuits and Architecture Design (Inderscience Publishers),Vol. 2 No. 2, 2016. (DOI: 10.1504/IJCAD.2016.10003038)
[23] S. L. Murotiya and Anu Gupta, “Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology,” International. Jounal of Electronics, Taylor & Francis, Sep. 2015. DOI:10.1080/00207217.2015.1082199 , SCI Indexed, (IMPACT FACTOR-0.459)
[22] Priya Gupta, Anu Gupta and Abhijit Asati, “ Ultra low power MUX based compressors for Wallace and Dadda multipliers in sub-threshold regime,” American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4, pp:702-716, Nov. 2015. (DOI: 10.3844/ajeassp.2015.702.716) (Impact Factor: 0.545)
[21] Priya Gupta, Anu Gupta and Abhijit Asati, " Leakage Immune Modified Pass Transistor based 8T-SRAM Cell in Sub-threshold Region," International Journal of Reconfigurable Computing, Hindavi publishing corporation, Volume 2015. (http://dx.doi.org/10.1155/2015/749816) (H Index: 10)-- Scopus Indexed
[20] Priya Gupta, Anu Gupta and Abhijit Asati "Power-Aware Design of Logarithmic Prefix Adders in Subthreshold Regime: A Comparative Analysis" Elsevier journal of Procedia Computer Science, Vol. 46, pp. 1401 – 1408, 2015.
[19] Snehlata Murotiya, Anu Gupta “Design of hardware efficient low power 2-bit Ternary ALU using CNTFETs”, International Journal of Electronics, Taylor & Francis, 2015, http://dx.doi.org/10.1080/00207217.2015.1082199 , SCI Indexed, (IMPACT FACTOR-0.459)
[18] Sneh Lata Murotiya and Anu gupta (2014), “A Novel Design of Ternary Full Adder using CNTFETs” Arabian Journal of Science and Engineering ,DOI 10.1007/s13369-014-1350-x, Springer, 2014 SCI Indexed, (IMPACT FACTOR-0.367)
[17] Priya Gupta, Anu Gupta and Abhijit Asati,"Design and implementation of N-bit sub-threshold Kogge Stone adder with improved power delay product," European Journal of Scientific Research, Volume 123, No 1, 106-116, June, 2014. (ISSN: 1450-216X/1450-202X) (Impact Factor: 0.713) -- SCImago Indexed
[16] Saumya Vij, Anu Gupta and Alok Mittal "An Operational Amplifier With Recycling Folded Cascode Topology And Adaptive Biaisng", International Journal of VLSI Design & Communication Systems(VLSICS), Volume 5, Number 4, August 2014
[15] Sneh lata Murotiya and Anu gupta (2014), "Design of content-addressable memory cell using CNTFETs", International Journal of Electronics Letters ,Taylor & Francis, 2014 DOI: 10.1080/21681724.2014.911368 , SCI Indexed, , (IMPACT FACTOR-0.751)
[14] Sneh Lata Murotiya and Anu gupta (2013), “Design of CNTFET-based Radiation hardened Latches” European Journal of Scientific Research, Scientific Research Platform , Volume 117 Issue 1, 2013. (IMPACT FACTOR-0.713)
[13] Sneh lata Murotiya and Anu gupta (2013), " Design of CNTFET based 2-bit ternary ALU for nano-electronics, International Journal of Electronics, Taylor & F.rancis, 2013, DOI: 10.1080/00207217.2013.828. SCI Indexed, (IMPACT FACTOR-0.751)
[12] Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Sub-threshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333
[11] Anu Gupta, Raj Singh Dua, " A Novel Ultra Low Power, High Impedance Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region", International Journal of New Innovations in Engineering and Technology (IJNIET), Vol. 1 Issue 3 February 2013, ISSN: 2319-6319, pp-93
[10] Sneh Lata Murotiya, Aravind Matta & Anu Gupta, "Performance Evalution Of CNTFET-Based Sram Cell Design", International Journal of Electrical and Electronics Engineering (IJEEE) ISSN (PRINT): 2231 – 5284, Vol-2, Iss-1, 2012
[9] Sachin Maheshwari, Amitoj Singh and Anu Gupta, “Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology”, “International Journal of Advances in Electronics Engineering, Vol.2 Issue 2, 2012.
[8] Anirban Chatterjee, Sankha Subhra Saha, Rishabh Gupta, Anu Gupta , “A Comparative Exploration of Sample and Hold architectures using Verilog AMS International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 5, May 2012, pp-260-264
[7] S. K. Sahoo, Anu Gupta, Abhijit R. Asati and Chandra Shekhar “A Novel Redundant Binary Number to Natural Binary Number Converter” Journal of Signal Processing Systems (Springer), Vol. 59, 2010, pp: 297-307(IMPACT FACTOR --0.551)
[6] Ashray Vinayak Gogte, Anu Gupta, “Low Power Temperature Compensated CMOS Current Reference”, International Journal of Recent Trends in Engineering, Vol 1, No. 3, May 2009, pp-287-289
[5] S K Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati and Anu Gupta, “Dual Channel Addition Based FFT Processor Architecture for Signal and Image Processing” , Int. J. High Performance Systems Architecture, Vol. 2, No. 1, 2009, pp-35-45.
[4] Maneesh Menon, Robin Paul Prakash, Anu Gupta, “Design of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topology”, International Journal of Recent Trends in Engineering, Vol.1, No. 4, May 2009
[3] Nikhil Bhattar, Anu Gupta, “On-chip resistors can make a stable current reference”, Potentials, IEEE, Volume: 27, Issue: 1, 2008, pp-31-36, SCI INDEXED , (Impact Factor-- 4.934)
[2] Anu Gupta, Bipin Naraynan Kulkarni, “Automation of Clock Distribution Network Design for Digital Integrated Circuits using Divide and Conquer technique” , Integration, the VLSI Journal, Vol. 39, issue 4, pp 407-419, ELSEVIER, 2006, pp-407-419. SCI Indexed, (IMPACT FACTOR --0.66)
[1] Anu Gupta, Chandra Shekhar, “Performance exploration of adder architectures for small to moderate-sized low power, high performance adders” , Journal of Microelectronics International, Emerald Publishing, Vol. 22 No. 3, 2005, pp-20-27 , Scopus Indexed, (IMPACT FACTOR --0.73)
Conferences:
1. 1. Anu Gupta, & Chandrashekhar, “Adder Architectures for fully static and complementary pass logic designs” , Proceedings of the national seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec. 10-11, 2000, pp-140-145
2. Anu Gupta, & Chandrashekhar, “Design Exploration of Architecture for Optimal Adder Synthesis”, IETE Golden Jubilee Seminar on Electronic Design Automation: Issues and Challenges, April 26, 2003, pp-4-6
3. S K Sahoo, Chandra Shekhar, Anu Gupta, “A Compact Fast Parallel Multiplier Using Modified Equivalent Binary Conversion Algorithm”, Proceedings of VLSI Design and Test Workshop , Aug. 26-28, 2004
4. Arpit Kumar Gupta, Anu Gupta, “A Design Methodology for Efficient Design of fully differential OP AMP as a Voltage Buffer.”, IMS Conference-2006, Electronics Science Department, Kurukshetra university, Kurukshetra, February 17-18, 2006.
5. Anu Gupta, Ninad B Kothari, “Effect of Transistor Sizing in Design of an Energy Efficient 1-bit Full Adder Design using different Adiabatic Logic Circuit Techniques”, IMS Conference-2006, Electronics Science Department, Kurukshetra university, Kurukshetra, February 17-18, 2006
6. Tushar Uttarwar, Sanket Jain, Anu Gupta, Nitin Chaturvedi, “A High Performance, Low Power, Fully Differential Telescopic Amplifier”, Advances in Electronic System Design (AESD'08) conference, ATMIYA CONFERENCE CLUSTER 2008 (ACC '2008), November 20 - 23, 2008 at AITS, Rajkot (GUJARAT)
7. Sameer Somvanshi , S C Bose, Anu Gupta, “A novel sub-1 Volt Bandgap Reference with all CMOS”, Proceedings of the 12th WSEAS international conference on Circuits, Heraklion, Greece. World Scientific and Engineering Academy and Society Year of Publication, 2008 , pp-232-237
8. Ashray Vinayak Gogte, Anu Gupta, “A new temperature compensated CMOS current reference”, International conference on multimedia signal processing and communication technologies , 14 -16 March 2009 Zakir Husain college of Engineering & Technology , Aligarh muslim university
9. Gaurav Agarwal, Amit Singhal, Anu Gupta, Prayush Kumar, “Hardware Implementation of Delighting Module for Using it in a Digital Camera Chip”, Proceeding Of 13th IEEE VLSI Design And Test Symposium held on July 8-10, 2009, Bangalore, pp-96-104
10. Raj Dua, Sumeet Tiwana, Anu Gupta, “Ultra Low Power Digital to Analog Converter “,Progress In VLSI Design And Test 2009, Proceeding Of 13th IEEE VLSI Design And Test Symposium held on July 8-10, 2009, Bangalore, pp-271-279
11. Raj Singh Dua, Anu Gupta, “A Novel Ultra Low Power Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region for Virtual Instrumentation Systems”, National Conference On Virtual And Intelligent Instrumentation( NCVII-09), 13-14 Nov. 2009, BITS, Pilani , Rajasthan (best paper award)
12. Hariprasad Chandrakumar , Anu Gupta, “A Micropower Low-noise CMOS Neural Amplifier for Bio-medical Instrumentation”, National Conference On Virtual And Intelligent Instrumentation( NCVII-09), 13-14 Nov. 2009, BITS, Pilani , Rajasthan
13. Amit Agarkhed, Sharvil Patil, Anu Gupta, “Improved Implementation of CRL and SCRL Gates for Ultra-Low Power”, International conference on advances in recent technologies in communication and comutind, ARTCOM 2009, Technically Co-sponsored by the IEEE-Computational Intelligence Society, Kottayam, Kerala India., 27 - 28 Oct 2009 (paper is archived in the IEEE Xplore) Archived in IEEE EXPLORE (Impact Factor-- 4.934)
14. Sneh Lata Murotiya and Anu Gupta, “An Exploration of VLSI parallel Adder using Carbon NanoTube Field Effect Transistor,” Souvenir of National Conference on VLSI Design and Embedded Systems, CEERI, Pilani, pp-7A.5, October 12-14, 2011
15. Anu Gupta and Subhrojyoti Sarkar, “An Efficient High Frequency and Low Power Analog Multiplier in Current Domain,” Proceedings of 16th International Symposium, pp-1-9, VDAT 2012, Shibpur, India, July 1-4, 2012
16. Sivaram Prasad Kopparthy, Ishit Makwana, Anu Gupta, “Asynchronous 8-bit Pipelined ADC for Self-Triggered Sensor based Applications”, Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (Prime Asia), Dec 5-7, 2012, BITS-Pilani, Hyderabad Campus (paper is archived in the IEEE Xplore) (IMPACT FACTOR-4.934)
17. Sneh Lata Murotiya, Aravind Matta and Anu Gupta, “Performance evaluation of CNTFET based SRAM cell design.” Proc. of Inter National Conference on Electrical Engineering and Computer Science,”, May 12, 2012, Trivandrum, Kerala, pp-88-92
18. Sivaram Prasad Kopparthy, Ishit Makwana, Anu Gupta, “An Asynchronous 8-bit 5 MS/s Pipelined ADC , Jan 17-19, 2013, World Trade Center, Bangalore, India (paper is archived in the IEEE Xplore) (IMPACT FACTOR-4.934)
19. Tushar Uttarwar, Sanket Jain, Anu Gupta, “Design of a High Performance, Low Power, Fully Differential Telescopic Amplifier using Stable Common-Mode Feedback Circuit”, International Joint Conferences on Computer, Information and Systems Sciences and Engineering, December 5th – 13th, 2008, Sponsored by University of Bridgeport, Technically co-sponsored by IEEE Computer Society and Communications Society
20. Ashutosh Mehra, Anu Gupta, Sharvil Patil, Abhishek Mehra, “A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers”, International conference on advances in recent technologies in communication and computing, ARTCOM 2009, Technically Co-sponsored by the IEEE-Computational Intelligence Society, Kottayam, Kerala India., 27 - 28 Oct 2009 (paper is archived in the IEEE Xplore) (IMPACT FACTOR-4.934)
21. Vivek Gupta, Anu Gupta, Nitin Chaturvedi, Abhijit Asati, “A Novel Technique for Improvement of Power Supply Rejection Ratio in Amplifer Circuits “, International Conference on Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09. December 28-29, 2009, Trivandrum, Kerala, India (paper is archived in the IEEE Xplore), pp-756 – 758 . (IMPACT FACTOR-4.934)
22. Maneesh Menon, Karan Dhall, Anu Gupta, Nitin Chaturvedi , “High bandwidth Low Power Cascaded Three Stage Amplifier with Multi-path Nested Miller Compensation for high performance IC Applications”, International Conference on Recent Trends in Information, Telecommunication and Computing – ITC 2010, March 12-13, 2010 in Kochi, Kerala, India, Paper is archived in the IEEE Xplore, pp-9 – 12. (IMPACT FACTOR-4.934)
23. Anu Gupta, Jithin P. Thomas, K.R.S.N. Kumar, Vamsidhar Addanki, Nitin Chaturvedi, “Hardware Implementation of a biometric fingerprint Identification System”, International Joint Journal Conference in Computer, Electronics and Electrical, CEE 2010
24. Gaurav Jain,Vaibhav Gogte, Shivani Bathla, Anu Gupta, “An Exploration of Efficient Architecture for Double Data Rate SDRAM for a High Performance Implementation, International Conference on Advances in Electrical & Electronics (AEE), Dec 20-21, 2011 in Noida, India
25. Himadri Raghav, Sachin Maheshwari, Anu Gupta, “A Comparative Analysis of Power & Delay Optimize Digital Logic Families for High Performance System Design", International Conference on Electronic Systems (ICES 2011), NIT Rourkela
26. Anu Gupta, Mohammad Waqar Ahamed, Abhishek Dhir , Ravish Soni, Neeraj Kumar Sharma, “ Novel Method To Implement High Frequency All Digital Phase-Locked Loop On FPGA”, International Conference on VLSI & Communication Systems , SAINTGITS College of Engineering, Pathamuttom, Kotyam, Kerala, 2011
27. Gaurav Jain, Vaibhav Gogte, Shivani Bathla, Anu Gupta, “An Exploration of Efficient Architecture for Double Data Rate SDRAM for a High Performance Implementation, “International Conference on Advances in Electrical & Electronics (AEE), Noida, India , Dec 20-21 2011, Paper ID-AET_AEE_507
28. Sachin Maheshwari, Amitoj Singh and Dr. Anu Gupta, "Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology", Proc. of the Int. Conf. on Advances in Computer, Electronics and Electrical Engineering (ICACEEE-2012), March 25-27, Mumbai, pp. 91-95, 2012. (ISBN: 978-981-07-1847-3). (Also published in UACEE International Journal of Advances in Electronics Engineering, Vol. 2, Issue 2, pp. 39-43, ISSN 2278 - 215X [Online]
29. Sneh Lata Murotiya, Aravind Matta, Anu Gupta, “Performance evaluation of CNTFET based SRAM cell design.” Proc.of International Conference on Electrical Engineering and Computer Science,” pp-88-92, May 12, 2012, Trivandrum, Kerala
30. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, " Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT), Jaipur, India, 2013.
31. Sachin Maheshwari, Himadri Singh Raghav and Dr. Anu Gupta, " Characterization of Logical Effort for Improved Delay" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT) Jaipur, India, 2013.
32. Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Sub-threshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June , 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333 (Print)
33. Sachin Maheshwari, Himadri Singh Raghav and Dr. Anu Gupta, " Characterization of Logical Effort for Improved Delay" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 108–117, 2013. (© Springer-Verlag Berlin Heidelberg 2013).
34. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, "Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 185–193, 2013. (© Springer-Verlag Berlin Heidelberg, 2013
35. Sneh Lata Murotiya, Anu Gupta, "CNTFET Based Design of Content Addressable Memory Cells", 4th IEEE International Conference on Computer and Communication Technology (ICCCT – 2013), MNNIT Allahabad, pp.1-4, Sep.20-22, 2013. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
36. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register”, 1st IEEE International Conference on Advanced Electronic Systems (ICAES – 2013), CEERI Pilani, pp. 180-183, Sep. 21-23, 2013. . Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
37. Sneh Lata Murotiya, Anu Gupta, “DESIGN AND ANALYSIS OF CNTFET BASED D FLIP-FLOP”, presented in ICCS – 2013, BKBIET Pilani and published in IJECET, vol.4, issue 7 pp. 144-149, 2013.
38. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based DTCAM cell”, IEEE Conference INDICON – 2013, IIT Mumbai. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
39. Priya Gupta, Akshay Kumar Sharma, Pratishtha Dehadray, Anu Gupta “Design and Implementation of low power TG Full Adder design in subthreshold regime” IEEE International Conference on Intelligent Interactive Systems and Assistive Technologies, August 2-3, 2013, Coimbatore, INDIA. Paper archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
40. Priya Gupta, Ishan Munje, Nikhil Kaswan , Anu Gupta , Abhijit Asati “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime” Selected to be published on IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), March 20th-21st 2014, Tamilnadu . Research Institute, Pilani, September 21-23, 2013 Paper archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
41. Nikhil Kaswan , Ishan Munje, Yash Kothari , Priya Gupta, Anu Gupta “Implementation of high speed energy efficient 4-bit binary CLA based incrementer /decrementer” in 2013 International Conference on Advanced Electronic Systems (ICAES), Sept. 21-23 2013, CEERI Pilani. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
42. Abhilash K N, Shakthi Bose, Anu Gupta, " Abhilash K N, Shakthi Bose, Anu Gupta, " A High Gain, High CMRR Two-Stage Fully Differential Amplifier Using gm/Id technique for Bio-medical Applications", IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
43. Siddharth Malhotra , Abhinav Mishra, Rakesh B R , Anu Gupta, "Frequency Compensation in Two-Stage Operational Amplifiers for Achieving High 3-dB Bandwidth” IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013. Paper is archived in the IEEE Xplore (IMPACT FACTOR-4.934)
44. Ganesh Raj, Ankur Gupta , Dr. Anu Gupta, " Self timed High speed 8-bit SAR ADC in 0.35um", IEEE Conference INDICON – 2013, IIT Mumbai . Paper is archived in the IEEE Xplore (IMPACT FACTOR-4.934) DOI: 10.1109/INDCON.2013.6726028
45. Jaskaran Singh Grover , Anu Gupta ,"Studying Crosstalk Trends for Signal Integrity on Interconnects using Finite Element Modeling", COMSOL Conference 2013 October 17 - 18, 2013, Bangalore
International Conferences (Abroad)46. Cherin Joseph, Anu Gupta, “A novel hardware efficient Digital Neural Network architecture implemented in 130nm technology”, The 2nd International Conference on Computer and Automation Engineering (ICCAE), 2010, Paper is archived in the IEEE Xplore, pp-82-87 (IMPACT FACTOR-4.934)
47. Priya Gupta, Ishan Munje, Nikhil Kaswan, Anu Gupta and Abhijit Asati, “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime” IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), 20-21 March 2014, Tamilnadu.
48. Priya Gupta, Anu Gupta and Abhijit Asati, "Power-Aware Design of Logarithmic Prefix Adders in Sub-Threshold Regime: A Comparative Analysis" International Conference on Information and Communication Technologies (Under TEQIP Phase-II)-ICICT, 3-5 December 2014, Kochi.
49. Snehlata Murotiya, Anu Gupta , Sparsh Vashishtha " Novel Design of Ternary Magnitude Comparator using CNTFETs", 11th IEEE India Conference, INDICON-2014, 11-13th dec. 2014, Yashada, Pune
50. Vineet Kumar, Abhijit Asati, Anu Gupta, “An Iris Localization Method for Noisy Infrared Iris Images" IEEE International Conference on Signal and Image Processing Applications (ICSIPA) Kuala Lumpur, Malaysia, 18-21 October, 2015.
51. Priya Gupta, Divya Samnani, Anu Gupta, Abhijit Asati, "Design and ASIC Implementation of Column Compression Wallace/Dadda Multiplier in Sub-Threshold Regime," Proceedings of the 9th INDIACom;INDIACom - 2015, 2nd International Conference on “Computing for Sustainable Global Development”, New Delhi, India, 11– 13 March, 2015.
52. Priya Gupta, Ishan Munje, Nikhil Kaswan, Anu Gupta and Abhijit Asati, “Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime” International Jounal. of Circuits and Architecture, Design -Inderscience Publishers, 2015)
53. Deepansh Dubey, Anu Gupta: A Low Power Low Noise Bio-Amplifier with Tunable Gain, IEEE International Conference on Electrical, Computer and Communication Technologies (EESCO 2015), VIIT, Vishakhapatnam, 24th-25th January 2015.
54. D. Dubey, Anu Gupta, "A Low Power Low Noise Amplifier for Biomedical Applications", Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on , 5-7 March 2015, SVS College of Engineering, Coimbatore, pp:1-6, DOI:10.1109/ICECCT.2015.7226134 , Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.935)
55. D. Dubey, Anu Gupta ,"Improvement of Operational Amplifier in Subthreshold Region using Forward Body Bias", IEEE India Conference (INDICON), Jamia Millia Islamia, New Delhi, India from 17-20 December 2015 Paper archived in the IEEE Xplore,. Paper is archived in the IEEE Xplore, pp-82-87 (IMPACT FACTOR-4.934)
56. Priya Gupta, Anu Gupta and Abhijit Asati, “Ultra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-Threshold Regime” American Journal of Engineering and Applied Sciences, Nov. 2015, pp:702-716,DOI: 10.3844/ajeassp.2015.702.716
57. V. Kumar, A. Asati, and A. Gupta, “Iris Localization Based on Integro-Differential Operator for Unconstrained Infrared Iris Images”, International Conference on Signal Processing, Computing and Control, JUIT, Waknaghat, India, Sept. 2015.
58. V. Kumar, A. Asati, and A. Gupta, “An Iris Localization Method for Noisy Infrared Iris Images”, IEEE International Conference on Signal and Image Processing Applications, Kuala Lumpur, Malaysia, Oct. 2015.
59. Rajiv Gupta, Leela Krishna Kondepati, Anu Gupta, " Tender Evaluation by Visual Decision Support System", IIE and URUAE International Conference, March 20-21, 2016 Mauritius
60. Rajiv Gupta, Anu Gupta, Advait Nair, "To predict the impact of passive architecture on the temperature conditions inside a building using ANN" , The 7th International renewable Energy Congress, March 22 – 24, 2016, Hammamet, Tunisia, SCOPUS indexed.
61. Karan Raj Singh, Anu Gupta,"A Hardware optimized Low power RNM Compensated three stage Operational amplifier with Embedded Capacitance Multiplier Compensation" 2nd IEEE International Conference on VLSI Systems, Architecture, Technologies and Applications (VLSI SATA 2016), Amrita School of Engineering, Bengaluru, India, 10 - 12 January 2016 , Paper in the IEEE Xplore DOI: 10.1109/VLSI-SATA.2016.7593038,Scopus indexed.
62. Priyesh Shukla, Anu Gupta, "Quad-NMOS Cross-coupling for Linearity Enhancement in High Frequency Continuous-time OTA-C Filters with IM3 Below -70 dB", 6th International Conference on Information and Electronics Engineering (ICIEE 2017), February 22-24, 2017, Singapore, Scopus indexed
63. Priyesh Shukla, Anu Gupta, "Current-Mode PMOS Capacitance Multiplier", International Conference on Inventive Systems and Control (ICISC 2017) ,19-20 January 2017 , JCT College of Engineering and Technology, Coimbatore, IEEE sponsored, Scopus indexed
64. Prakhar kumar, Srijan Rastogi, and AnuGupta, "Novel design of linear low power Gm-C based voltage controlled filter with programmable gain", International Conference Of Science Technology & Management (ICSTM-2017), 24 september 2017, Bengaluru.
65. BrahmbhattViralkumarKishorkumar, AnuGupta ,"Demonstration of CORDIC based Digitally assisted analog using 12 bit pipelined ADC ", International Conference Of Science Technology & Management (ICSTM-2017), 24 september 2017, Bengaluru.
66. Abheek Gupta, Anu Gupta, and Rajiv Gupta, " Power and Area Efficient Intelligent Hardware Design for Water Quality Applications", 1st International Conference on on Microelectronic Devices and Technologies (MicDAT '2018) 20-22 June 2018, Barcelona, Spain
67. Kalpraj Vaidya , Anu Gupta, and Rajiv Gupta, "High Gain, High Bandwidth Fully Differential low voltage OpAmp Design Using Self-Cascode MOSFET with Adaptive Bias and Common mode Feedback", 1st International Conference on on Microelectronic Devices and Technologies (MicDAT '2018) 20-22 June 2018, Barcelona, Spain